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| IC42S16400A Document Title 1M x 16Bit x 4 Banks (64-MBIT) SDRAM Revision History Revision No 0A History Initial Draft Draft Date February 19,2004 Remark The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR039-0A 02/19/2004 1 IC42S16400A 1M x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES * Single 3.3V ( 0.3V) power supply * High speed clock cycle time -6: 166MHz, -7: 133MHz<3-3-3> * Fully synchronous operation referenced to clock rising edge * Possible to assert random column access in every cycle * Quad internal banks contorlled by A12 & A13 (Bank Select) * Byte control by LDQM and UDQM for IC42S16400A * Programmable Wrap sequence (Sequential / Interleave) * Programmable burst length (1, 2, 4, 8 and full page) * Programmable CAS latency (2 and 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * LVTTL compatible inputs and outputs * 4,096 refresh cycles / 64ms * Burst termination by Burst stop and Precharge command * Package 400mil 54-pin TSOP-2 and 60ball(64M) VF-BGA * Pb(lead)-free package is available DESCRIPTION The IC42S16400A are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 1,048,576 x 16 x 4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture and clock frequency up to 166MHz for -6. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOP-2 and 60ball(64M) VF-BGA. PIN CONFIGURATIONS 54-Pin TSOP-2 VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A 60-BALL VF-BGA ( 64M SDRAM ) 7 6 5 4 3 2 1 VDD A1 A2 A10 BA0 CS CAS WE NC DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 VDD A3 A0 BA1 NC RAS LDQM VDD NC VSSQ VDDQ DQ4 VSSQ VDDQ DQ0 A4 A5 A7 A9 NC CLK UDQM NC NC VDDQ VSSQ DQ11 VDDQ VSSQ DQ15 VSS A6 A8 A11 CKE NC NC NC DQ8 DQ9 DQ10 DQ12 DQ13 DQ14 VSS R P N M L K J H G F E D C B A PIN DESCRIPTIONS A0 - A11 BA0,BA1 DQ0 - DQ15 CLK CKE CS RAS CAS WE LDQM,UDQM VDD/VSS VDDQ/VSSQ NC Address Bank Address Data Input/Output Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Power Supply/Ground Data Output Power/Ground No Connection Row Address : RA0 - RA11, Column Address : CA0 - CA7 Auto-precharge flag : A10 Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Multiplexed data input / output pin The system clock input.All other inputs are registered to the SDRAM on the rising edge of CLK Controls internal clock signal and when deactivated,the SDRAM will be one of the states among power down,suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM RAS,CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Power supply for internal circuits and input buffers Power supply for output buffers No Connection Integrated Circuit Solution Inc. DR039-0A 02/19/2004 3 IC42S16400A FUNCTIONAL BLOCK DIAGRAM CLK CKE Clock Generator Address Mode Register Row Decoder Row Address Buffer & Refresh Counter Bank D Bank C Bank B Bank A Sense Amplifier Command Decoder CS RAS CAS WE Control Logic Input & Output Buffer Latch Circuit Column Address Buffer & Burst Counter Column Decoder & Latch Circuit DQM Data Control Circuit DQ 4 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A ABSOLUTE MAXIMUM RATINGS(1) Symbol VDD VDDQ Parameters Rating Unit V V V V mA W C C VI VO IO PD TOPT TSTG Supply Voltage (with respect to VSS) -0.5 to +4.6 Supply Voltage for Output (with respect to VSSQ) -0.5 to +4.6 Input Voltage (with respect to VSS) -0.5 to VDD+0.5 Output Voltage (with respect to VSSQ) -1.0 to VDDQ+0.5 Short circuit output current 50 Power Dissipation (TA = 25 C) 1 Operating Temperature Storage Temperature 0 to +70 -65 to +150 Notes: 1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC RECOMMENDED OPERATING CONDITIONS (At TA = 0 to +70C unless otherwise noted) Symbol VDD VDDQ VIH VIL Parameter Supply Voltage Supply Voltage for DQ High Level Input Voltage (all Inputs) Low Level Input Voltage (all Inputs) Min. 3.0 3.0 2.0 -0.3 Typ. 3.3 3.3 -- -- Max. 3.6 3.6 VDD + 0.3 +0.8 Unit V V V V CAPACITANCE CHARACTERISTICS (At TA = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0V , unless otherwise noted) Symbol CIN CCLK CI/O Parameter Input Capacitance, address & control pin Input Capacitance, CLK pin Min. 2.5 2.5 4.0 Max. 3.8 3.5 6.5 Unit pF pF pF Data Input/Output Capacitance Integrated Circuit Solution Inc. DR039-0A 02/19/2004 5 IC42S16400A DC ELECTRICAL CHARACTERISTICS (At TA = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0V , unless otherwise noted) Symbol Parameter ICC1(1) Operating Current Test Condition One Bank active, Burst Length=1 tRC = tRC (min.) tCLK = tCLK (min.) CKE < VIL (MAX) Speed CAS latency = 3 -6(42S16400A) -7(42S16400A) Min. -- -- Max. 95 85 Unit mA mA ICC2P ICC2PS ICC2N(2) ICC2NS ICC3P ICC3PS ICC3N(2) ICC3NS ICC4 Precharge Standby Current (In Power-Down Mode) Precharge Standby Current (In Non Power-Down Mode) Active Standby Current (In Power-Down Mode) Active Standby Current (In Non Power-Down Mode) Operating Current (In Burst Mode) Auto-Refresh Current Self-Refresh Current Input Leakage Current (Inputs) ICC5 ICC6(3, 4) IIL IOL VOH VOL -6 -7 CKE < VIL (MAX) CLK < VIL (MAX) -6 -7 CS > VCC -0.2V tCK = 15 ns -6 CKE > VIH (MIN) -7 CS > VCC -0.2V CKE < VIL (MAX) -6 CKE > VIH (MIN) All input signals are stable. -7 CKE < VIL (MAX) tCK = 10 ns -6 -7 CKE < VIL (MAX) CLK < VIL (MAX) -6 -7 CS > VCC -0.2V tCK = 15 ns -6 CKE > VIH (MIN) -7 CS > VCC -0.2V CKE < VIL (MAX) -6 CKE > VIH (MIN) All input signals are stable. -7 All Banks active CAS latency = 3 -6(42S16400A) Burst Length=1 -7(42S16400A) tCK = tCK (MIN) tRC = tRC (MIN) -6 tCLK = tCLK (MIN) -7 CKE < 0.2V -6 -7 0V < VIN < VDD (MAX) Pins not under test = 0V tCK = 15 ns -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -5 -5 2.4 -- 2 2 1 1 20 20 15 15 7 7 5 5 30 30 25 25 130 100 150 130 1 1 5 5 -- 0.4 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A V V Output Leakage Current (I/O pins) High Level Output Voltage Low Level Output Voltage Output is disabled DQ# in H - Z., 0V < VOUT < VDD (MAX) IOUT = -2 mA IOUT = +2 mA Notes: 1. ICC(max) is specified at the output open condition. 2. Input signals are changed one time during 30ns. 6 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A AC TEST CONDITIONS (At TA = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0V , unless otherwise noted) Parameter AC input Levels (VIH /VIL ) Input timing reference level /Output timing reference level Input rise and fall time Output load condition Rating 2.0 / 0.8 1.4 1 50 Unit V V ns pF Output Load Conditions VDDQ VOUT VDDQ Z = 50 50PF Device Under Test Integrated Circuit Solution Inc. DR039-0A 02/19/2004 7 IC42S16400A AC ELECTRICAL CHARACTERISTICS (At TA = 0 ~ 70C, VDD = VDDQ = 3.3 0.3V, VSS = VSSQ = 0V , unless otherwise noted) -6 Symbol tCK3 tCK2 tAC3 tAC2 tCH tCL tCKE tCKH tAS tAH tCMS tCMH tDS tDH tOH3 tOH2 tLZ tHZ tRC tRAS tRCD tRP tRRD tDPL tT tRSC tPDE tSRX tREF Parameter CLK Cycle Time CLK to valid output delay(1) CLK high pulse width CLK low pulse width CKE setup time CKE hold time Address setup time Address hold time Command setup time Command hold time Data input setup time Data input hold time Output data hold time(1) CLK to output in low - Z CLK to output in H - Z ROW cycle time ROW active time RAS to CAS delay Row precharge time Row active to active delay Data in to precharge Transition time Mode reg. set cycle Power down exit setup time Self refresh exit time -7 Max. -- -- 5 6 -- -- -- -- -- -- -- -- -- -- -- -- -- 5 -- 100,000 -- -- -- -- 10 -- -- -- 64 Min. 7.5 10 -- -- 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 2.7 3 0 2.7 67.5 45 20 20 15 15 1 10 7.5 7.5 -- Max. -- -- 5.4 6 -- -- -- -- -- -- -- -- -- -- -- -- -- 5.4 -- 100,000 -- -- -- -- 10 -- -- -- 64 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Min. CAS Latency = 3 CAS Latency = 2 CAS Latency = 3 CAS Latency = 2 6 7.5 -- -- 2.5 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.8 2.5 2.5 0 2.5 60 42 18 15 12 12 1 10 7.5 7.5 -- CAS Latency = 3 CAS Latency = 2 Refresh Time Notes: 1. if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter. 8 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Basic Features and Function Description Simplified State Diagram Self Refresh try en it ex LF SE Mode Register Set MRS IDLE LF SE REF AUTO Refresh CK E E CK ROW ACTIVE BS T ACT Power Down CKE CKE T BS Active Power Down ad Re W rit e Au Write to p rec with har ge h wit rge ad cha Re Pre to Au re co ve r y Write (Write recovery) Read PRE W rit e WRITE SUSPEND CKE CKE WRITE Read (write recovery) Write READ CKE CKE READ SUSPEND Write with Auto Precharge R Auto ead w Pre ith cha rge rge cha P re E( PR ith e te w arg Wri Prech uto (writA e re cov ery) ter min atio n ) Read with Auto Precharge WRITE A SUSPEND CKE CKE WRITE A CKE READ A CKE READA SUSPEND POWER ON Precharge Precharge Automatic sequence Manual input Note: After the AUTO refresh operation, precharge operation is performed automatically and enter the IDLE state Integrated Circuit Solution Inc. DR039-0A 02/19/2004 PR E (P r ech arg e m ter tio ina n) 9 IC42S16400A COMMAND TRUTH TABLE Symbol DESL NOP MRS ACT READ READA WRIT WRITA PRE PALL BST REF SELF Command Device deselect No operation Mode register set Bank activate Read Read with auto precharge Write Write with auto precharge Precharge select bank Precharge all banks Burst stop CBR (Auto) refresh Self refresh L : Low level V : Valid Data input CKE n-1 n H H H H H H H H H H H H H X X X X X X X X X X X H L CS H L L L L L L L L L L L L RAS X H L L H H H H L L H L L CAS X H L H L L L L H H H L L WE X H L H H H L L L L L H H BA X X L V V V V V V X X X X A11 A10 A9-A0 X X L V L H L H L H X X X X X V V V V V V X X X X X Notes: H : High level X : High or Low level (Don't care) DQM TRUTH TABLE CKE Symbol ENB MASK Command Data Write / Output Enable Data Mask / Output Disable n-1 H H n X X DQM L H CKE TRUTH TABLE Symbol -- -- -- REF SELF -- -- -- Command Clock suspend mode entry Clock suspend Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit Current State Activating Any Clock suspend Idle Idle Self refresh Idle Power down CKE n-1 n H L L H H L L H L L L H H L H H L H CS X X X L L L H X X RAS X X X L L H X X X CAS X X X L L H X X X WE X X X H H H X X X Addreess X X X X X X X X X 10 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A OPERATION COMMAND TABLE(1) Current State Command Idle DESL NOP or BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation NOP or Power-Down(2) NOP or Power-Down(2) Illegal(3) Illegal(3) Row Active NOP Refresh or Self-Refresh(4) Mode Register Set NOP NOP Begin read : Determine AP(5) Begin write : Determine AP(5) CS H L L L L L L L H L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L RAS X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X H H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code Row Active X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 Illegal(3) Precharge(6) Illegal Illegal Continue burst to end -> Row active Continue burst to end -> Row active Burst stop -> Row active Term burst, new read : Determine AP(7) Term burst, start write : Determine AP(7, 8) X Op-Code Read X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code Illegal(3) Term burst, precharging Illegal Illegal Continue burst to end -> write recovering Continue burst to end -> write recovering Burst stop -> Row active Term burst, start read : Determine AP(7, 8) Term burst, new write : Determine AP(7) Write X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 Illegal(3) Term burst, precharging(9) Illegal Illegal Continue burst to end -> Precharging Continue burst to end -> Precharging X Op-Code Read With AutoPrecharge Illegal Illegal(11) Illegal(11) Illegal(3) Illegal(11) Illegal Illegal X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code Integrated Circuit Solution Inc. DR039-0A 02/19/2004 11 IC42S16400A OPERATION COMMAND TABLE(continue) Current State Command Write with auto precharge Operation CS RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 Precharging Row activating Write recovering DESL NOP BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Continue burst to end -> write recovering with auto precharge H Continue burst to end -> write recovering with auto precharge L Illegal Illegal(11) Illegal(11) Illegal(3, 11) Illegal(3, 11) Illegal Illegal Nop -> Enter idle after tRP Nop -> Enter idle after tRP Nop -> Enter idle after tRP Illegal(3) Illegal(3) Illegal(3) Nop -> Enter idle after tRP Illegal Illegal Nop - > Enter row active after tRCD Nop - > Enter row active after tRCD Nop - > Enter row active after tRCD Illegal(3) Illegal(3) Illegal(3, 9) Illegal(3) Illegal Illegal Nop -> Enter row active after tDPL Nop -> Enter row active after tDPL Nop -> Enter row active after tDPL Start read, Determine AP(8) New write, Determine AP Illegal(3) Illegal(3) Illegal Illegal L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L X Op-Code X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code 12 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A OPERATION COMMAND TABLE(continue) Current State Command Write recovering with auto precharge Operation Nop -> Enter precharge after tDPL Nop -> Enter precharge after tDPL Nop -> Enter precharge after tDPL CS H L L L L L L L L H L L L L H L L L L RAS X H H H H L L L L X H H L L X H H H L CAS X H H L L H H L L X H L H L X H H L X WE X H L H L H L H L X X X X X X H L X X Address X X X BA, CA, A10 BA, CA, A10 BR, RA BA, A10 X Op-Code Auto Refreshing Mode register setting DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Illegal(3 ,8, 11) Illegal(3,11) Illegal(3, 11) Illegal(3, 11) Illegal Illegal Nop Enter idle after tRC Nop Enter idle after tRC X X X Illegal Illegal Illegal Nop -> Enter idle after 2 Clocks Nop -> Enter idle after 2 Clocks X X X X X Illegal Illegal Illegal X X Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. 2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address(BA), depending on the state of that bank. 4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode. All input buffers except CKE will be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Must mask preceding data which don't satisfy tDPL . 10. Illegal if tRRD is not satisfied. 11. Illegal for single bank, but legal for other banks in multi-bank devices. Integrated Circuit Solution Inc. DR039-0A 02/19/2004 13 IC42S16400A CKE RELATED COMMAND TRUTH TABLE(1) Current State Self-Refresh (S.R.) Operation INVALID, CLK (n - 1)would exit S.R. CKE n-1 n (2) CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS X X H H L X X H H L X H H L X X X X X X H L L L X H L L L X X X X X CAS X X H L X X X H L X X H L X X X X X X X X H L L X X H L L X X X X X WE X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X Address X X X X X X X X X X X X X X X X -- X X -- -- -- X Op - Code Self-Refresh Recovery Self-Refresh Recovery(2) Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After tRC Idle After tRC Illegal Illegal Begin clock suspend next cycle(5) Begin clock suspend next cycle(5) Illegal Illegal Exit clock suspend next cycle(2) Maintain clock suspend INVALID, CLK (n - 1) would exit P.D. EXIT P.D. -> Idle(2) Maintain power down mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Power-Down (P.D.) Both Banks Idle Auto-Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Self-Refresh(3) Refer to operations in Operative Command Table Power-Down(3) Any state other than listed above Refer to operations in Operative Command Table Begin clock suspend next cycle(4) Exit clock suspend next cycle Maintain clock suspend H L L L L L H H H H H H H H L L H L L H H H H H H H H H H L H H L L X H H H H L H H H H L L L L H L X H L H H H H H L L L L L X H L H L -- -- -- X Op - Code X X X X X Notes: 1. H : Hight level, L : low level, X : High or low level (Don't care). 2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 3. Power down and Self refresh can be entered only from the both banks idle state. 4. Must be legal command as defined in Operative Command Table. 5. Illegal if tSREX is not satisfied. 14 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Initiallization Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs. 2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all bank. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode regiser. After these sequence, the SDRAM is in idle state and ready for normal operation. CAS Latency CAS latency is the most critical parameter being set. It tells the device how many clocks must elapse before the data will be available. The value is determined by the frequency of the clock and the speed grade of the device. The value can be programmed as 2 or 3. Burst Length Burst Length is the number of words that will be output or input in read or write cycle. After a read burst is completed, the output bus will become high impedance. The burst length is programmable as 1, 2, 4, 8 or full page. Wrap Type (Burst Sequence) The wrap type specifies the order in which the burst data will be addressed. The order is programmable as either "Sequential" or "Interleave". The method chosen will depend on the type of CPU in the system. Programming the Mode Register The mode register is programmed by the mode register set command using address bits A13 through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power. The mode register has four fields; Options : A13 through A7 CAS latency : A6 through A4 Wrap type : A3 Burst length : A2 through A0 Following mode register programming, no command can be asserted befor at least two clock cycles have elapsed. Integrated Circuit Solution Inc. DR039-0A 02/19/2004 15 IC42S16400A MODE REGISTER 13 12 11 000 13 12 00 11 0 10 0 10 0 9 0 9 0 8 0 8 0 7 1 7 0 6 4 LTMODE 5 3 WT 2 1 BL 0 Burst Read and Burst Write X = Don't care 6 5 4 3 2 1 0 JEDEC Standard Test Set Bits2 - 0 WT = 0 WT = 1 1 000 1 001 010 Burst length 011 100 101 110 111 Wrap type 0 1 2 4 8 R R R Fullpage 2 4 8 R R R R Sequential Interleave Bits 6-4 000 001 010 Latency mode 011 100 101 110 111 CAS Iatency R R 2 3 R R R R Remark R : Reserved 16 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Burst Length and Sequence Burst of Two Starting Address (column address A0, binary) 0 1 Sequential Addressing Sequence (decimal) 0, 1 1, 0 Interleave Addressing Sequence (decimal) 0, 1 1, 0 Burst of Four Starting Address (column address A1 - A0, binary) 00 01 10 11 Sequential Addressing Sequence (decimal) 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 Interleave Addressing Sequence (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 Burst of Eight Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Sequential Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1 ,2 4, 5, 6, 7, 0, 1, 2, 3 5, 6 ,7, 0, 1, 2, 3, 4 6, 7 ,0 ,1 ,2 ,3 ,4 ,5 7, 0, 1, 2, 3, 4, 5, 6 Interleave Addressing Sequence (decimal) 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 17 IC42S16400A Address Bits of Bank-Select and Precharge Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (Activate command) A12 0 0 1 1 A13 0 1 0 1 Result Select Bank A "Activate " command Select Bank B "Activate" command Select Bank C "Activate" command Select Bank D "Activate" command Row A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (Precharge command) A10 0 0 0 0 1 A12 A13 Result 0 0 1 1 X 0 1 0 1 X Precharge Bank A Precharge Bank B Precharge Bank C Precharge Bank D Precharge All Banks X: Don't care 0 1 Co1. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 (CAS strobes) Disable Auto-Precharge (End of Burst) Enable Auto - Precharge (End of Burst) A12 0 0 1 1 A13 0 1 0 1 Result Enable Read/Write commands for Bank A Enable Read/Write commands for Bank B Enable Read/Write commands for Bank C Enable Read/Write commands for Bank D 18 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Precharge The precharge command can be asserted anytime after tRAS(min.) is satisfied. Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows. PrechargeE T0 CLK Command Read T1 T2 T3 T4 T5 T6 Burst lengh=4 T7 PRE CAS latency = 2 DQ Q0 Q1 Q2 Q3 Hi - Z Command CAS latency = 3 DQ Read PRE Q0 Q1 Q2 Q3 Hi - Z (tRAS is satisfied) In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of clocks can be calculated by dividing tDPL(min.) with the clock cycle time. In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is valid. In the following table, minus means clocks before the reference; plus means time after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL((min.) + tDPL((min.) Integrated Circuit Solution Inc. DR039-0A 02/19/2004 19 IC42S16400A Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. In the write cycle, tDAL(min.) must be satisfied before asserting the next activate command to the bank being precharged. When using auto precharge in the read cycle, knowing when the precharge starts is important because the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. Once auto precharge has started, an activate command to the bank can be asserted after tRP has been satisfied. A Read or Write command without auto - precharge can be terminated in the midst of a burst operation. However, a Read or Write command with auto - precharge can not be interrupted by the same bank commands before the entire burst operation is completed. Therefore use of the same bank Read, Write, Precharge or Burst Stop command is prohibited during a read or write cycle with auto - precharge. It should be noted that the device will not respond to the Auto - Precharge command if the device is programmed for full page burst read or write cycles. The timing when the auto precharge cycle begins depends both on both the CAS Iatency programmed into the mode register and whether the cycle is read or write. Read with Auto Precharge During a READA cycle, the auto precharge begins one clock earlier (CL = 2) or two clocks earlier (CL = 3) than the last word output. READ with AUTO PRECHARGE Burst lengh = 4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK No New Command to Bank B Command READA B Auto precharge starts CAS latency = 2 DQ QB0 QB1 QB2 QB3 Hi - Z No New Command to Bank B Auto precharge starts Command CAS latency = 3 DQ Remark READA means READ with AUTO PRECHARGE QB0 QB1 QB2 QB3 Hi - Z READA B 20 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of tDPL(min.) after the last data word input to the device. WRITE with AUTO PRECHRGE Burst lengh = 4 T0 CLK Command WRITA B AUTO PRECHARGE starts T1 T2 T3 T4 T5 T6 T7 T8 CAS latency = 2 DQ DB0 DB1 DB2 tDPL Hi - Z_ DB3 Command CAS latency = 3 DQ AUTO PRECHARGE starts WRITA B tDPL Hi - Z DB0 DB1 DB2 DB3 Remark WRITA means WRITE with AUTO Precharge In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means clocks after the reference. CAS latency 2 3 Read -1 -2 Write + tDPL((min.) + tDPL((min.) Integrated Circuit Solution Inc. DR039-0A 02/19/2004 21 IC42S16400A Read / Write Command Interval Read to Read Command Interval During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction. READ to READ Command Interval Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Read A Read B Command DQ QA0 QB0 QB1 QB2 QB3 Hi-Z_ 1 cycle Write to Write Command Interval During a write cycle, when a new Write command is asserted, the previous burst will terminate and the new burst will begin with a new write command. WRITE will be interrupted by another WRITE. Each write command can be asserted in every clock without any restriction. WRITE to WRITE Command Interval Burst lengh=4, CAS latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Write A Write B Command DQ QA0 QB0 QB1 QB2 QB3 Hi-Z_ 1 cycle 22 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT. WRITE to READ Command Interval Burst lengh=4 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK 1 cycle Command CAS latency=2 Hi-Z WRITE A Read B DQ DA0 QB0 QB1 QB2 QB3 Command Write A Read B CAS latency=3 DQ DA0 Hi-Z QB0 QB1 QB2 QB3 Read to Write Command Interval During a read cycle, READ can be interrupted by WRITE. DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data bus must be Hi-Z using DQM before Write. Integrated Circuit Solution Inc. DR039-0A 02/19/2004 23 IC42S16400A READ to WRITE Command Interval CAS latency=2 T8 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read Write DQM DQ Hi-Z D0 D1 D2 D3 1 cycle T0 T1 T2 T3 T4 T5 T6 T7 Burst length=8, CAS latency=2 T8 T9 CLK Command Read Write DQM DQ Q0 Q1 Q2 Hi-Z is necessary D0 D1 D2 example: Burst length=4, CAS latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Command Read Write DQM DQ Q2 Hi-Z is necessary D0 D1 D2 24 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A BURST Termination There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command. BURST Stop Command During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command. During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to HiZ at the same clock with the burst stop command. Burst Termination T0 T1 T2 T3 T4 T5 Burst lengh=X, CAS Intency=2,3 T7 T6 CLK BST Command Read CAS latency=2 DQ Q0 Q1 Q2 Hi-Z CAS latency=3 DQ Q0 Q1 Q2 Hi-Z Remark BST: Burst stop command T0 T1 T2 T3 T4 T5 Burst lengh=X, CAS latency=2,3 T7 T6 CLK BST Command Write CAS latency=2,3 Q0 DQ Q0 Q1 Q2 Hi-Z_ Remark BST: Burst command Integrated Circuit Solution Inc. DR039-0A 02/19/2004 25 IC42S16400A PRECHARGE TERMINATION PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. When CAS latency is 2, the read data will remain valid until one clock after the precharge command. When CAS latency is 3, the read data will remain valid until two clocks after the precharge command. Precharge Termination in READ Cycle Burst lengh= X T8 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Read PRE tRP ACT CAS latency=2 DQ Q0 Q1 Q2 Q3 Hi-Z command Read PRE tRP ACT CAS latency=3 DQ Q0 Q1 Q2 Q3 Hi-Z 26 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Precharge Termination in WRITE Cycle During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high at the same clock as the precharge command. This will mask the invalid data. PRECHARGE TERMINATION in WRITE Cycle Burst lengh = X T8 T0 CLK Command CAS latency = 2 DQM DQ D0 Write T1 T2 T3 T4 T5 T6 T7 PRE ACT D1 D2 D3 D4 tRP Hi - Z command CAS latency = 3 DQM Write PRE ACT DQ D0 D1 D2 D3 D4 Hi - Z tRP Integrated Circuit Solution Inc. DR039-0A 02/19/2004 27 IC42S16400A Mode Register Set T0 CLK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CKE t RSC CS RAS CAS WE BS0,1 A10 Address Key ADD DQM t RP DQ Hi-Z Precharge Command All Banks Mode Register Set Command Command 28 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A AC Parameters for Write Timing (1 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CH t CL t CMS t CMH t CK2 Begin Auto Precharge Begin Auto Precharge Bank A Bank B CKE t CKS t CKH CS RAS CAS WE *BS0 A10 t AS tAH ADD DQM tRCD DQ t RRD tRC tDAL tDS t DH t DPL t RP QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 Activate Write with Activate Write with Activate Command Auto Precharge Command Auto Precharge Command Bank A Command Bank A Command Bank B Bank B Bank A Write without Auto Precharge Command Bank A Precharge Command Bank A Activate Command Bank A Activate Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 29 IC42S16400A AC Parameters for Write Timing (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK t CL t CH t CK3 t CMS t CMH Begin Auto Precharge Begin Auto Precharge Bank A Bank B t CKH CKE t CKS CS RAS CAS WE *BS0 A10 t AS t AH ADD DQM tRCD DQ t RRD RC t DAL tDS t DH t DPL t RP QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Write with Activate Write with Auto Precharge Command Auto Precharge Command Bank B Command Bank A Bank B Activate Command Bank A Write without Auto Precharge Command Bank A Precharge Command Bank A Activate Command Bank A BS1="L", Bank C,D = Idle 30 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A AC Parameters for Read Timing (1 of 2) Burst Length=2, CAS Latency=2 T0 CLK tCH tCL T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 tCK2 tCMS t CMH Begin Auto Precharge Bank B t CKH CKE tCKS CS RAS CAS WE *BS0 A10 tAS tAH ADD tRRD tRAS tRC DQM t AC2 tLZ tAC2 tOH QAa0 t RCD tHZ tOH QAa1 QBa0 tRP tHZ QBa1 DQ Hi-Z Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 31 IC42S16400A AC Parameters for Read Timing (2 of 2) Burst Length=2, CAS Latency=3 T0 CLK t CH tCL t CK3 t CMS t CMH Begin Auto Precharge Bank B T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CKE tCKS t CKH CS RAS CAS WE *BS0 A10 t AH t AS ADD t RRD t RAS t RC t RP DQM t RCD tAC3 tLZ tAC3 tOH tHZ tOH QAa1 QBa0 t HZ DQ Hi-Z QAa0 QBa1 Activate Command Bank A Read Command Bank A Activate Command Bank B Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A BS1="L", Bank C,D = Idle 32 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Power on Sequence and Auto Refresh (CBR) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE High level is required t RSC Minimum of 8 Refresh Cycles are required CS RAS CAS WE BS0, 1 A10 Address Key ADD DQM High Level is Necessary t RP t RC DQ Hi-Z Precharge Inputs Command All Banks must be stable for 200us 1st Auto Refresh Command 2nd Auto Refresh Command Mode Register Set Command Command Integrated Circuit Solution Inc. DR039-0A 02/19/2004 33 IC42S16400A Clock Suspension During Burst Read (Using CKE) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM t HZ DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Read Command Bank A Clock Suspended 1 Cycle Clock Suspended 2 Cycles Clock Suspended 3 Cycles BS1="L", Bank C,D = Idle 34 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Clock Suspension During Burst Read (Using CKE) (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM t HZ DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A Read Command Bank A Clock Suspended 1 Cycle Clock Suspended 2 Cycles Clock Suspended 3 Cycles BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 35 IC42S16400A Clock Suspension During Burst Write (Using CKE) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM DQ Hi-Z DAa0 DAa1 DAa2 DAa3 Activate Command Bank A Clock Suspended 1 Cycle Write Command Bank A Clock Suspended 2 Cycles Clock Suspended 3 Cycles BS1="L", Bank C,D = Idle 36 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Clock Suspension During Burst Write (Using CKE) (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 CLK t CK3 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM DQ Hi-Z DAa0 DAa1 DAa2 DAa3 Activate Command Bank A Clock Suspended 1 Cycle Write Command Bank A Clock Suspended 2 Cycles Clock Suspended 3 Cycles BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 37 IC42S16400A Power Down Mode and Clock Mask Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t t CKS CKH t CKS CKE VALID CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 Activate Command Bank A ACTIVE STANDBY Read Command Bank A Clock Mask Start Clock Mask End Precharge Command Power Down Mode Entry Precharge Standby Power Down Mode Entry Power Down Mode Exit Power Down Mode Exit Command BS1="L", Bank C,D = Idle 38 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Auto Refresh (CBR) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0, 1 A10 RAa ADD RAa CAa DQM t RP t RC t RC Q0 Q1 Q2 Q3 DQ Hi-Z Precharge CBR Refresh Command Command All Banks CBR Refresh Command Activate Read Command Command BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 39 IC42S16400A Self Refresh (Entry and Exit) CLK can be Stopped** T0 T1 T2 T3 T4 T5 T6 T7 CLK T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 t SRX t SRX t CKS CKE t CKS CS RAS CAS WE *BS0 A10 ADD t RC t RC DQM DQ Hi-Z All Banks must be idle Self refresh Entry Self Refresh Exit Self Refresh Entry Self Refresh Exit Activate Command BS1="L", Bank C,D = Idle Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High 40 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Random Column Read (Page With Same Bank) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa RAa RAd ADD RAa CAa CAb CAc RAd CAd DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 QAd0 QAd1 QAd2 QAd3 Precharge Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Precharge Activate Read Command Command Command Bank A Bank A Bank A BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 41 IC42S16400A Random Column Read (Page With Same Bank) (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa RAd ADD RAa CAa CAb CAc RAd CAd DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAb0 QAb1 QAc0 QAc1 QAc2 QAc3 Activate Command Bank A Read Command Bank A Read Read Command Command Bank A Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A BS1="L", Bank C,D = Idle 42 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Random Column Write (Page With Same Bank) (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 Ra Rd ADD Ra Ca Cb Cc Rd Cd DQM DQ Hi-Z Da0 Da1 Da2 Da3 Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Dd2 Dd3 Activate Command Bank B Write Command Bank B Write Write Command Command Bank B Bank B Precharge Activate Write Command Command Command Bank B Bank B Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 43 IC42S16400A Random Column Write (Page With Same Bank) (1 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 Ra Rd ADD Ra Ca Cb Cc Rd Cd DQM DQ Hi-Z Da0 Da1 Da2 Da3 Db0 Db1 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1 Activate Command Bank B Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B Activate Command Bank B Write Command Bank B BS1="L", Bank C,D = Idle 44 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Random Row Read (Interleaving Banks) (1 of 2) Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 ADD t t AC2 t RP DQM RCD DQ Hi-Z QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1 Activate Command Bank B Read Command Bank B Activate Command Bank A Precharge Active Command Command Bank B Bank B Read Command Bank A Read Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 45 IC42S16400A Random Row Read (Interleaving Banks) (2 of 2) Burs tLength=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 ADD t t RCD AC3 t RP DQM DQ Hi-Z QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 Activate Command Bank B Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Precharge Command Command Bank B Bank A BS1="L", Bank C,D = Idle 46 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Random Row Write (Interleaving Banks) (1 of 2) Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 ADD DQM t RCD t DPL t RP DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QAb0 QAb1 QAb2 QAb3 QAb4 Activate Command Bank A Write Command Bank A Activate Command Bank B Precharge Active Command Command Bank A Bank A Write Command Bank B Write Command Bank A Precharge Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 47 IC42S16400A Random Row Write (Interleaving Banks) (2 of 2) Burst Length=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 ADD RBa DQM t DPL t RP t DPL DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBa0 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBb7 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Precharge Write Command Command Bank B Bank A BS1="L", Bank C,D = Idle 48 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Read and Write Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa CAb CAc DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 DAb0 DAb1 DAb3 QAc0 QAc1 QAc3 Activate Command Bank A Write Command Bank A The Write Data Write Command is Masked with a Bank A Zero Clock latency Read Command Bank A The Read Data is Masked with Two Clocks Latency BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 49 IC42S16400A Read and Write Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa CAb CAc DQM Hi-Z QAa0 QAa1 QAa2 QAa3 DQ DAb0 DAb1 DAb3 QAc0 QAc1 QAc3 Activate Command Bank A Read Command Bank A Write The Write Data Read Command is Masked with a Command Bank A Bank A Zero Clock Latency The Read Data is Masked with Two Clock Latency BS1="L", Bank C,D = Idle 50 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Interleaved Column Read Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD Ra Cb Ra Ca Cb Cc Cb Cd DQM t RCD t AC2 DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3 Activate Command Bank A Read Read Read Activate Read Read Read Command Command Command Command Command Command Command Bank A Bank A Bank B Bank B Bank B Bank B Bank B Precharge Command Bank A Precharge Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 51 IC42S16400A Interleaved Column Read Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD Ra Ca Ra Ca Cb Cc Cb DQM t RCD t RRD t AC3 DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Read Read Read Precharge Precharge Command Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Bank A BS1="L", Bank C,D = Idle 52 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Interleaved Column Write Cycle (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD Ra Ca Ra Ca Cb Cc Cb Cb DQM t RCD t RP t DPL t Hi-Z RRD DQ DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 DBb0 DBb1 DBc0 DBc1 DAb0 DAb1 DBd0 DBd1 DBd2 DBd3 Activate Write Write Write Write Write Activate Command Command Command Command Command Command Command Bank B Bank B Bank A Bank A Bank B Bank B Bank A Precharge Command Bank A Write Command Bank B Precharge Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 53 IC42S16400A Interleaved Column Write Cycle (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD Ra Ca Ra Ca Cb Cc Cb Cd DQM t RCD t DPL t DPL t Hi-Z RRD t RP DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBb0 QBb1 QBc0 QBc1 QAb0 QAb1 QBd0 QBd1 QBd2 QBd3 Activate Command Bank A Write Command Bank A Activate Command Bank B Write Write Write Write Write Command Command Command Command Command Bank A Bank B Bank B Bank B Bank B Precharge Command Bank A Precharge Command Bank B BS1="L", Bank C,D = Idle 54 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Auto Precharge after Read Burst (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb Rc ADD Ra Ca Ra Ca Cb Rb Cb Rc Cc DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 Activate Read Activate Read with Command Command Command Auto Precharge Bank A Bank A Bank B Command Bank B Read with Auto Precharge Command Bank A Activate Command Read with Bank A Auto Precharge Command Read with Activate Bank B Auto Precharge Command Command Bank B Bank A BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 55 IC42S16400A Auto Precharge after Read Burst (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Cb Rb RBb Cb DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 Activate Command Bank A Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Activate Command Bank B Write with Auto precharge Command Bank B BS1="L", Bank C,D = Idle 56 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Auto Precharge after Write Burst (1 of 2) Burst Length=4, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb Rc ADD Ra Ca Ra Ca Cb Rb Cb Rc Cc DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 Activate Write Write with Activate Command Command Command Auto Precharge Command Bank A Bank B Bank A Bank B Activate Write with Activate Command Auto Precharge Command Bank A Command Bank B Write with Bank A Auto Precharge Write with Bank A Auto Precharge Command Bank B Start Auto Precharge Bank A BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 57 IC42S16400A Auto Precharge after Write Burst (2 of 2) Burst Length=4, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Cb Rb RBb Cb DQM DQ Hi-Z QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QBa2 QBa3 QAb0 QAb1 QAb2 QAb3 QBb0 QBb1 QBb2 QBb3 Activate Command Bank A Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Read with Auto Precharge Command Bank A Activate Command Bank B Write with Auto precharge Command Bank B BS1="L", Bank C,D = Idle 58 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Full Page Read Cycle (1 of 2) Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Rb DQM t RP DQ Hi-Z QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+51QBa+6 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Precharge Command Bank B Burst Stop Command Activate Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 59 IC42S16400A Full Page Read Cycle (2 of 2) Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Rb DQM DQ Hi-Z QAa QAa+1 QAa+2 QAa-2 QAa-1 QAa QAa+1 QBa0 QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 Activate Command Bank A Read Command Bank A Activate Command Bank B Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Full page burst operation does not teminate when Precharge the burst length is satisfied; Command the burst counter increments Bank B and continues bursting beginning with the starting Burst Stop address Command Activate Command Bank B BS1="L", Bank C,D = Idle 60 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Full Page Write Cycle (1 of 2) Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Rb DQM t BDL DQ Hi-Z QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa QAa+1 QBa QBa+1 QBa+2 QBa+3 QBa+4 QBa+5 QBa+6 Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Data is ignored Precharge Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Burst Stop Command Activate Command Bank B BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 61 IC42S16400A Full Page Write Cycle (2 of 2) Burst Length=Full Page, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ca Ra Ca Rb DQM tBDL Data is ignored. DQ Hi-Z DAa DAa+1 DAa+2 DAa+3 DAa-1 DAa DAa+1 DBa DBa+1 DBa+2 DBa+3 DBa+4 DBa+5 Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Write Command Bank B Full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address Precharge Command Bank B Burst Stop Command Activate Command Bank B BS1="L", Bank C,D = Idle 62 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Full Page Random Column Read Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE BS A10 Ra Ra Rb ADD Ra Ra Ca Ca Cb Cb Cc Cc Rb t RP DQM DQ Hi-Z QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2 Activate Command Bank A Activate Command Bank B Read Command Bank B Read Command Bank A Read Command Bank B Read Command Bank A Read Command Bank B Precharge Command Bank B (Bank D) (Precharge Termination) Activate Command Bank B Read Command Bank A BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 63 IC42S16400A Full Page Random Column Write Burst Length=Full Page, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE CS RAS CAS WE *BS0 A10 Ra Ra Rb ADD Ra Ra Ca Ca Cb Cb Cc Cc Rb t RP DQM DQ Hi-Z QAa0 QBa0 QAb0 QAb1 QBb0 QBb1 QAc0 QAc1 QAc2 QBc0 QBc1 QBc2 Activate Command Bank A Activate Command Bank B Write Command Bank B Write Command Bank A Write Command Bank B Write Command Bank A Write Command Bank B Precharge Command Bank B (Bank D) (Precharge Termination) Write Data is masked Activate Command Bank B Write Command Bank A BS1="L", Bank C,D = Idle 64 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A Precharge Termination of a Burst (1 of 2) Burst Length=8, CAS Latency=2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK2 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 RAa RAb RAc ADD RAa CAa RAb CAb RAc CAc t DPL t RP t RP t RP DQM DQ Hi-Z QAa0 QAa1 QAa2 Da3 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 Activate Command Bank A Write Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Precharge Termination of a Write Burst. Write data is masked. Precharge Termination of a Read Burst. BS1="L", Bank C,D = Idle Integrated Circuit Solution Inc. DR039-0A 02/19/2004 65 IC42S16400A Precharge Termination of a Burst (2 of 2) Burst Length=8, CAS Latency=3 T0 T1 T2 T3 T4 T5 T6 T7 CLK t CK3 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CKE High CS RAS CAS WE *BS0 A10 RAa RAb RAc ADD RAa CAa RAb CAb RAc t DPL t RP t RAS t RP DQM t RCD DQ Hi-Z DAa0 DAa1 QAb0 QAb1 QAb2 QAb3 Activate Command Bank A Write Command Bank A Precharge Command Bank A Activate Command Bank A Read Command Bank A Activate Command Bank A Activate Command Bank A Write Data is masked Precharge Termination of a Write Burst. Precharge Termination of a Read Burst. BS1="L", Bank C,D = Idle 66 Integrated Circuit Solution Inc. DR039-0A 02/19/2004 IC42S16400A ORDERING INFORMATION Commercial Range: 0C to 70C Speed (ns) 6 Order Part No. IC42S16400A-6T IC42S16400A-6TG IC42S16400A-6BG IC42S16400A-7T IC42S16400A-7TG IC42S16400A-7BG Package 400mil TSOP-2 400mil TSOP-2(Pb-free) 60Ball VF-BGA(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) 60Ball VF-BGA(Pb-free) 7 ORDERING INFORMATION Industrial Temperature Range: -40C to 85C Speed (ns) 6 Order Part No. IC42S16400A-6TI IC42S16400A-6TIG IC42S16400A-6BIG IC42S16400A-7TI IC42S16400A-7TIG IC42S16400A-7BIG Package 400mil TSOP-2 400mil TSOP-2(Pb-free) 60Ball VF-BGA(Pb-free) 400mil TSOP-2 400mil TSOP-2(Pb-free) 60Ball VF-BGA(Pb-free) 7 Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. DR039-0A 02/19/2004 67 |
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